The present invention relates to a nonvolatile semiconductor memory device (hereafter referred to as an "EEPROM") with which erasing and writing can be performed electrically and memory contents can be held even after power is cut off.
FIG. 2 is a schematic block diagram of an EEPROM in the prior art.
This EEPROM is provided with m bit lines BL.sub.1, BL.sub.2, . . . BL.sub.m that are positioned parallel to one another and n word lines WL.sub.1, WL.sub.2, . . . WL.sub.n positioned perpendicular to the bit lines BL.sub.1 to BL.sub.m.
A memory cell 10.sub.ij is connected at the intersection of each bit line BL.sub.i (i=1 to m) and each word line WL.sub.j (j=1 to n). The memory cells 10.sub.ij are each constituted of a field effect transistor having a floating gate.
The drain of the field effect transistor constituting each memory cell 10.sub.ij is connected to the bit line BL.sub.i while its control gate is connected to the word line WL.sub.j, with its source commonly connected to a source line SL.
Each bit line BL.sub.i is structured so that a voltage VSS (=0V) is applied to it by an n-channel MOS transistor (hereafter referred to as an "NMOS") 20.sub.i for switching. The electrical charge at each bit line BL.sub.i is discharged by a common clear signal DC. In addition, each bit line BL.sub.i is connected to an input/output buffer 40 and a sense amplifier 50 via an NMOS 30.sub.i for switching.
Furthermore, the EEPROM in the prior art is provided with a row decoder 60 and a column decoder 70. The row decoder 60 decodes a row address AX that has been provided and activates one word line WL.sub.j that corresponds to the row address AX. The column decoder 70 decodes a column address AY that has been provided and selects one bit line BL.sub.i by setting the NMOS 30.sub.i corresponding to the column address AY to an ON state to connect it to the input/output buffer 40 and the sense amplifier 50.
Moreover, the EEPROM in the prior art is provided with m page latches 80.sub.1, 80.sub.2, . . . 80.sub.m for batch data writing in one-word memory cells 10.sub.ij to 10.sub.mj during a data writing. Page latches 80.sub.i are provided for each bit line BL.sub.i and all the page latches are structured almost identically to one another.
The page latch 80.sub.1, for instance, is provided with a flipflop (hereafter referred to as an "FF") 80A which is constituted of p-channel MOS transistors (hereafter referred to as "PMOS") 81 and 82 and NMOS's 83 and 84.
For instance, the FF 80A provided at the page latch 80.sub.1 is connected to the bit line BL.sub.1 by an NMOS 85 which is turned on or off by a load signal LD. In addition, the page latch 80.sub.1 is provided with NMOS's 86 and 87 which are connected in series for controlling a bit line voltage VBL applied to the bit line BL.sub.1. The NMOS 86 is Turned on or off by the level of the voltage of the data stored at the FF 80A whereas the NMOS 87 is ON/OFF controlled by a writing voltage PVW.
The individual page latches 80.sub.i are commonly connected to a control voltage generating unit 90, and are each structured so that source voltages VW and VS are supplied to the FF 80A and that the load signal LD, the bit line voltage VBL and the right voltage PVW are provided with specific timing.
The EEPROM in the prior art structured as described above operates as described below when specific data are to be written in memory cells 10.sub.11, to 10.sub.m1, selected with, for instance, the word line WL.sub.1.
First, in order to batch erase the data stored in the one-word memory cells 10.sub.11 to 10.sub.m1 connected to the word line WL.sub.1 , the voltage VSS is applied to the source line SL and a voltage VPP (=15V) is applied to the word line WL.sub.1 from the row decoder 60. Since this causes an electrical charge to be accumulated at the floating gates of the individual memory cells 10.sub.11 to 10.sub.m1 the threshold voltage Vt at these memory cells 10.sub.11 to 10.sub.m1 increases. The increase in the threshold voltage Vt sets all the memory cells 10.sub.11 to 10.sub.m1 in an OFF state, and consequently, the stored data are erased.
After the data stored in the one-word memory cells 10.sub.11 to 10.sub.m1 are batch erased, the source line SL is cut off from the supply line of the voltage VSS and is set in a floating state.
Then a load signal LD at a high logic level (hereafter referred to as "H" level) indicating source voltage VW=voltage VCC (=3V), source voltage VS=voltage VSS, bit line voltage VBL=voltage VSS and writing voltage PVW=voltage VSS is provided to the FF 80A.
When address "1" is provided for the column address AY and the bit line BL.sub.1 is selected by a bit selection signal Y.sub.1 in this state, data DT.sub.1 to be written in the memory cell 10.sub.11 are input to the selected bit line BL.sub.1 via the input/output buffer 40. With this, the data DT.sub.1 are stored at the FF 80A of the page latch 80.sub.1 connected to the bit line BL.sub.1.
Likewise, when addresses "2," "3," . . . , "m" are provided for the column address AY and the bit lines BL.sub.2, BL.sub.3, . . . BL.sub.m are sequentially selected, data DT.sub.2, DT.sub.3, . . . , DT.sub.m are input to the selected bit lines BL.sub.2, BL.sub.3, . . . BL.sub.m respectively via the input/output buffer 40. This results in the data DT.sub.2 to DT.sub.m being stored at the FF's 80A of the individual page laches 80.sub.2 to 80.sub.m.
After the data DT.sub.i are stored in each page latch 80.sub.i, the load signal LD is set to a logically low level (thereafter referred to as "L" level) and the output from the column decoder 70 are all set to "L" level. This causes the NMOS's 30.sub.1 to 30.sub.m to enter an OFF state, and all the bit lines BL.sub.1 to BL.sub.m are cut off from the input/output buffer 40 and the sense amplifier 50 to enter a floating state.
Next, with each bit line BL.sub.i sustaining a floating state, the voltage VPP is applied to the supply lines through which the source voltage VW, the bit line voltage VBL and the writing voltage PVW are supplied. In addition, a voltage of -8V is applied to the word line WL.sub.1.
Then, the voltage VSS is applied to the bit lines BL.sub.i connected to the page latches 80.sub.i where data "1" are stored, and with the electrical charge accumulated at the floating gate of the memory cell 10.sub.1i held intact, the data "1" are written in the memory cell 10.sub.1i as a result.
In addition, the voltage VPP is applied to the bit line BL.sub.i connected to the page latch 80.sub.i where data "0" are stored, and with the electrical charge accumulated at the floating gates of the memory cells 10.sub.1i discharged, data "0" are written in the memory cells 10.sub.1i as a result.
Then, after the data DT.sub.1 to DT.sub.m are batch written in the one-word memory cells 10.sub.11 to 10.sub.m1 connected to the word line WL.sub.1, these data DT.sub.1 to DT.sub.m are sequentially read out and are compared with the contents in the page laches 80.sub.1 to 80.sub.m connected to the individual bit lines BL.sub.1 to BL.sub.m so that a so-called verification is performed to make a decision as to whether or not the data DT.sub.1 to DT.sub.m have been correctly written in the memory cells 10.sub.11 to 10.sub.m1.